PLLs are now widely used in communication systems, for example in the local oscillator LO for transmit and receive, signal detection in modems and receivers that use the PLL capability to track weak signals in noise, carrier recovery in signals with suppressed carrier modulation, and frequency modulators in RF transmitters.
1. The frequency synthesizer generates the high frequency signal at a controlled frequency, that is used in wireless communications and a wide variety of other applications. One widely used implementation of the synthesizer is the Phase-Lock Loop (PLL) system.
Another type of synthesizer implements a frequency loop using counters pair/computer system, uses a pair of counters to concurrently count a reference signal and the oscillator (VCO) signal, to compute the frequency deviation and correct it in a closed loop.
Of paramount importance in wireless is the effective use of the frequency spectrum. It is difficult to accommodate the growing number of users of wireless, while the frequency spectrum remains fixed and limited. An effective answer would be to better utilize the available spectrum, by transmitting more information (at higher bits/second rates) in the available spectrum (per each Hertz of bandwidth).
Frequency synthesizers are used as the LO, both for transmission and reception, and influence the achievable rate of communication (bits/second). The lower the phase noise of the synthesizer, the lower is the Bit Error Rate (BER) of the communication channel.
When there are errors in a communication, this requires the retransmission of messages and more overhead, resulting in an effective communication rate that is slower than the rated speed of a channel.
Thus, the phase noise limits the actual, effective communication speed. A low phase noise is required of a synthesizer for wireless communications.
The BER can also be reduced by increasing the signal to noise ratio, that is by transmitting at a higher power. This has other disadvantages, like shorter battery lifetime and possible damage to user from radio frequency radiation. Moreover, the cost for the transmitter is higher. Accordingly, for a given transmission rate and BER, by lowering the phase noise of the synthesizer it is possible to use a lower transmitted power, thus the battery lasts longer and the possible damage from radiation is reduced.
PLL devices have a finite, distinctive phase noise which influences the wireless system performance. Counter pair/computer devices have higher phase noise, because of the quantization error and other effects.
Frequency settling time is another important parameter in frequency synthesizers. Spread spectrum by frequency hopping is a proven method for effective spectrum utilization. The method requires that the synthesizer change the output frequency at predefined times. It takes time for the synthesizer to switch to a new frequency, with the time lost in the process limiting the performance of the communication channel.
Counter pair/computer devices have fast settling times, but their use in communication systems is limited because of phase noise and other limitations.
PLL devices have a long settling time. These devices are usually described as linear, closed loop systems. But the linear model holds only for the PLL in locked state. Prior to lock-on (during the transition to a new frequency for example) the device is nonlinear, with a complex process that presents difficulties in predicting its settling time.
Long-term frequency precision is another important requirement of frequency synthesizers. PLL devices have a definite advantage, since the oscillator phase is locked to the reference, and thus the output frequency is a precise multiple or submultiple of that reference. Counter pair/computer devices usually have a limited frequency precision, because of the truncation error and other limitations.
In a previous disclosure, as detailed in Israeli Patent No. 096351 and U.S. Pat. No. 5,182,528, the present applicant described a digital frequency synthesizer using a smart, computer-controlled closed loop to generate a precisely controlled frequency. The closed loop comprises the oscillator, the digital frequency measurement means, and a computer which is connected back to the oscillator.
This prior art synthesizer has a fast frequency switching, but requires a complex computation to find the frequency ratio, since the accumulated count may achieve large values. The ratio computation may take time to perform. Moreover, there are no provisions to achieve low phase noise, an important consideration in communication systems. There are no provisions to achieve phase coherency between the reference signal and the oscillator signal, another desired property in precise signal generators.
In a previous disclosure, as detailed in Israeli patent application No. 120552, the present applicant disclosed a PLL using a fast phase measurement unit which uses several bits of the reference and VCO counters.
A description of a frequency synthesizer using digital bus correction/normalization was published by the present inventor in the June 1998 issue of the "Microwave Journal" magazine, pp. 94-108, titled "A New PLL with Fast Settling Time and Low Phase Noise".
Subsequent research and design, together with a new approach to PLLs, resulted in a PLL with improved structure and method of operation with better performance, which are detailed in the present disclosure. Moreover, it was found that a phase-lock loop PLL using a fast phase difference measuring unit can be advantageously used to improve various communication system functions, as detailed below.
2. PLLs are now used for signal detection in modems and receivers. The PLL has very good performance in tracking weak signals in noise, relative to other detectors. At present, however, the PLL uses a slow phase detector, that takes at least one cycle of the input signal to measure the phase difference. Usually the low pass filter LPF in the loop is set to a slower time constant, so that the loop can only respond to phase errors that develop during several cycles of the input signal.
In practical applications, however, the PLL is required to respond faster. Fast phase changes occur because of multipath, Doppler and other factors. If the PLL cannot respond fast enough, then it may break lock-on, that is the communication is stopped for some time, until the PLL locks again. Cycle slipping or loss of lock result in errors in the communication. Where the transmitted signals have a fast modulation, that may preclude altogether the use of a PLL in the receiver, if a PLL cannot track these fast changing signals. PLLs can detect a signal in noise and their use is highly desirable in receivers or modems, provided their dynamic performance (ability to track a fast changing carrier) is satisfactory.
Thus, the slow response time limitations of prior art PLLs prevent their use in advanced communication applications.
3. Carrier recovery is now a problem in signals with suppressed carrier modulation. These signals are now widely used since, by eliminating the carrier signal, all the transmitted power is dedicated to the actual information. Thus, communication links achieve improved performance. Examples of this modulation are the biphase phase shift keying BPSK and the quadriphase phase shift keying QPSK.
The problem with carrier recovery is that a regular PLL cannot be used, since there is no carrier to lock on. The precise center frequency is required to demodulate the received signal. The center frequency is the frequency of the carrier that was phase modulated to begin with. Since there may be fluctuations in frequency or phase of the received signal because of propagation effects, it is necessary to track the center frequency in the receiver.
For BPSK, a squaring loop or a Costas loop may be used. Both systems perform in effect a squaring of the signal, to achieve a signal with the phase modulation removed. A PLL can then lock on that signal. More complex circuits are required for multiphase modulation.
The Costas loop is a modified PLL, and has the disadvantages of PLLs as detailed above. The squaring loop also uses a PLL to lock on to the carrier. A squaring loop has various disadvantages, for example there is the problem of implementing a precise square law transfer function that would not be affected by voltage, temperature etc. Moreover, a squaring loop performs a nonlinear processing of the signal together with interfering signals and noise, to generate new harmonics. These new harmonics may interfere with the operation of the PLL used for carrier recovery.
4. Clock recovery (or clock synchronization) is now a problem in digital signals transmission. The baseband signal contains both the data and the clock, and it is required to separate them to reconstruct the digital transmitted information. A modified PLL may be used for clock recovery, however PLLs at present have a limited performance that limits the performance of the clock recovery circuit.
5. Frequency modulation FM in RF transmitters. Various standards define a FM system, for example GSM or DECT. FM is simple to implement if a low performance is sufficient. In that case, a voltage controlled oscillator VCO can be simply modulated with the information to send. With the presently crowded spectrum, however, a higher performance is required.
Thus, an unstabilized VCO has drift problems, so that the signal from that VCO may not reach its corresponding receiver, but it may interfere with another channel. If a closed loop PLL is used, then it is difficult to modulate the frequency of the VCO, since the loop opposes these changes.
At present, one implementation uses a PLL that is alternately closed loop (to stabilize the VCO) and open loop (to enable frequency modulation of the VCO). This may achieve a low performance in both accounts: good VCO stabilization cannot be achieved since the loop is not closed all the time, and the phase of the VCO changes unexpectedly (because of FM and drift) between the lock-on time intervals. At the same time, modulation is only possible part of the time, so that part of the time the link is not usable for information transfer.
It is an objective of the present invention to provide for a PLL with improved performance, that can be used to address some of the problems in frequency synthesizers and other communication system functions.